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2.7 V to 5.5 V, <100 A, 8/10/12Bit nanoDACTM D/A, SPI Interface, SC70 Package
Preliminary Technical Data
FEATURES
6-lead SC70 package Power-down to <100 nA @ 3 V Micropower operation: max 100 A @ 5 V 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on-reset to 0 V with brownout detection 3 power-down functions Low power serial interface with Schmitt-triggered inputs On-chip output buffer amplifier, rail-to-rail operation SYNC interrupt facility Minimised Zero Code Error AD5601 Buffered 8-Bit Dac in SC70 B Version: 0.5 LSB INL AD5611 Buffered 10-Bit Dac in SC70 B Version: 0.5 LSB INL, A Version: 4 LSB INL AD5621 Buffered 12-Bit Dac in SC70 B Version: 1 LSB INL , A Version: 6 LSB INL
AD5601/AD5611/AD5621
FUNCTIONAL BLOCK DIAGRAM
Figure 1 RELATED DEVICES Part Number Description 2.7 V to 5.5 V, <100 A, 14 Bit nanoDACTM D/A, tiny SC70 Package
APPLICATIONS
Voltage Level Setting Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators
AD5641
GENERAL DESCRIPTION
The AD5601/AD5611/AD5621, members of the nanoDACTM family, are single, 8/10/12-bit buffered voltage out DAC that operates from a single 2.7 V to +5.5 V supply consuming <100 A at 5 V, and comes in a tiny SC70 package. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The AD5601/AD5611/AD5621 utilizes a versatile 3wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI(R), QSPITM, MICROWIRETM, and DSP interface standards. The reference for AD5601/AD5611/AD5621 is derived from the power supply inputs and thus gives the widest dynamic output range. The part incorporates a power-on-reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place to the device. The part contains a power-down feature that reduces the current consumption of the device to <100 nA at 3 V and provides software selectable output loads while in power-down mode. The part is put into power-down mode over the serial interface. The low power consumption of this part in normal operation makes it ideally suited to portable battery operated equipment.
The combination of small package and low power make these devices idea for level setting requirements such as generating bias or control voltages in space constrained and power sensitive applications
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD5601/AD5611/AD5621
PRODUCT HIGHLIGHTS
1. 2. Available in space saving 6-lead SC70 Package. Low power, single-supply operation. This part operates from a single 2.7 V to 5.5 V supply and typically consumes 0.2 mW at 3 V and 0.5 mW at 5 V, making it ideal for battery-powered applications. The on-chip output buffer amplifier allows the output of the DAC to swing rail-to-rail with a typical slew rate of 0.5 V/s. 4. 5. 6.
Preliminary Technical Data
Reference derived from the power supply. High speed serial interface with clock speeds up to 30 MHz. Designed for very low power consumption. The interface only powers up during a write cycle. Power-down capability. When powered down, the DAC typically consumes <100 nA at 3 V.
7. 3.
TABLE OF CONTENTS
AD5601/AD5611/AD5621--Specifications ................................. 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Description .............................. 7 Terminology ...................................................................................... 8 Typical Performance Characteristics ............................................. 9 General Description ....................................................................... 12 D/A Section................................................................................. 12 Resistor String ............................................................................. 12 Output Amplifier ........................................................................ 12 Serial Interface ............................................................................ 12 Input Shift Register .................................................................... 12 SYNC Interrupt .......................................................................... 13 Power-On-Reset ......................................................................... 13 Power-Down Modes .................................................................. 13 Microprocessor Interfacing....................................................... 13 Applications..................................................................................... 15 Choosing a Reference as Power Supply for AD5601/AD5611/AD5621 ....................................................... 15 Bipolar Operation Using the AD5601/AD5611/AD5621..... 15 Using AD5601/AD5611/AD5621 with an Opto-Isolated Interface ....................................................................................... 16 Power Supply Bypassing and Grounding................................ 16 Outline Dimensions ....................................................................... 17
REVISION HISTORY
Revision PrB: Preliminary Version
Rev. PrB | Page 2 of 17
Preliminary Technical Data AD5601/AD5611/AD5621--SPECIFICATIONS
AD5601/AD5611/AD5621
Table 1. VDD = 2.7 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted
Parameter STATIC PERFORMANCE AD5601 Resolution Relative Accuracy2 Differential Nonlinearity2 AD5611 Resolution Relative Accuracy3 Differential Nonlinearity2 AD5621 Resolution Relative Accuracy4 Differential Nonlinearity2 B Version1 Min Typ Max Unit Test Conditions/Comments
8 0.5 1
Bits LSB LSB
B Grade Guaranteed Monotonic by Design.
10 0.5 4.0 1
Bits LSB LSB LSB
B Grade A Grade Guaranteed Monotonic by Design.
12 1 6 1
Bits LSB LSB LSB
B Grade A Grade Guaranteed Monotonic by Design.
Zero Code Error Offset Error Full-Scale Error Gain Error Zero Code Error Drift Gain Temperature Coefficient
0.2 0.125 0.01 0.04 5.0 2.0
mV % of FSR LSB % of FSR V/C ppm of FSR/C VDD 18 V s V/s pF pF nV/Hz nV-s nV-s mA
All 0s Loaded to DAC Register.
All 1s Loaded to DAC Register.
Output CHARACTERISTICS5 Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Output Noise Spectral Density Noise Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short Circuit Current LOGIC INPUTS Input Current
1 2
0 8 0.5 470 1000 120 TBD 10 0.5 1 20
Code 1/4 to 3/4 RL = RL = 2 k DAC code=TBD , 10 kHz DAC code=TBD 0.1-10Hz Bandwidth 1 LSB Change Around Major Carry.
VDD = +3/5 V
1
A
Temperature ranges are as follows: B Version: -40C to +125C, typical at 25C. Linearity calculated using a reduced code range. 3 Linearity calculated using a reduced code range. 4 Linearity calculated using a reduced code range. 5 Guaranteed by design and characterization, not production tested.
Rev. PrB | Page 3 of 17
AD5601/AD5611/AD5621
Parameter VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = +4.5 V to +5.5 V VDD = +2.7 V to +3.6 V IDD (All Power-Down Modes) VDD = +4.5 V to +5.5 V VDD = +2.7 V to +3.6 V POWER EFFICIENCY IOUT/IDD B Version1 Min Typ Max 0.8 0.6 1.8 1.4 3 2.7 5.5 100 70 0.2 0.05 TBD 1 1 Unit V V V V pF V A A A A %
Preliminary Technical Data
Test Conditions/Comments VDD = +5 V VDD = +2.7 V VDD = +5 V VDD = +2.7 V
All Digital Inputs at Zero or VDD DAC Active and Excluding Load Current VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND ILOAD = 2 mA. VDD = +5 V
Rev. PrB | Page 4 of 17
Preliminary Technical Data TIMING CHARACTERISTICS
AD5601/AD5611/AD5621
Table 2. VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.
Parameter t17 t2 t3 t4 t5 t6 t7 t8 t9
t4
SCLK
Limit6 33 13 12 13 5 4.5 0 33 13
t2 t3
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min
t1
Test Conditions/Comments SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time SYNC Rising Edge to next SCLK Fall Ignore
t9
t8
t7 t6 t5
04611-A-002
SYNC
DIN
D15
D14
D2
D1
D0
D15
D14
Figure 2. Timing Diagram
6 7
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency is 30 MHz.
Rev. PrB | Page 5 of 17
AD5601/AD5611/AD5621 ABSOLUTE MAXIMUM RATINGS
Table 3. TA = 25C, unless otherwise noted
Parameter VDD to GND Digital Input Voltage to GND VOUT to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature SC70 Package JA Thermal Impedance JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD Rating -0.3 V to + 7.0 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +125C -65C to +160C 150C 332C/W 120C/W 215C 220C 2.0 kV
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Model AD5601BKS AD5611BKS AD5611AKS AD5621BKS AD5621AKS
Temperature Range -40OC to 125 OC -40OC to 125 OC -40OC to 125 OC -40 C to 125 C -40OC to 125 OC
O O
Description 0.5 LSB INL 0.5 LSB INL 4.0 LSB INL 1.0 LSB INL 6.0 LSB INL
Package Options KS-6 KS-6
KS-6 KS-6 KS-6
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrB | Page 6 of 17
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTION
SYNC 1 SCLK 2
04611-A-003
AD5601/AD5611/AD5621
5 GND TOP VIEW DIN 3 (Not to Scale) 4 VDD
AD5641
6 VOUT
Figure 3. AD5601/AD5611/AD5621-1 SC70 (Top View)
Table 4. Pin Function Descriptions
Mnemonic VDD VOUT SYNC Function Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and VDD should be decoupled to GND. Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 16th clock cycle unless SYNC is taken high before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Ground Reference Point for All Circuitry on the Part.
SCLK DIN GND
Rev. PrB | Page 7 of 17
AD5601/AD5611/AD5621 TERMINOLOGY
Relative Accuracy For the DAC, relative accuracy or Integral Nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 2. Differential Nonlinearity Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 3. Zero-Code Error Zero-code error is a measure of the output error when zero code (0000Hex) is loaded to the DAC register. Ideally the output should be 0 V. The zero-code error is always positive in the AD5601/AD5611/AD5621 because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV. A plot of zero-code error vs. temperature can be seen in Figure 6. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (FFFF Hex) is loaded to the DAC register. Ideally the output should be VDD - 1 LSB. Full-scale error is expressed in percent of full-scale range. A plot of full-scale error vs. temperature can be seen in Figure 6. Gain Error
Preliminary Technical Data
This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Total Unadjusted Error Total Unadjusted Error (TUE) is a measure of the output error taking all the various errors into account. A typical TUE vs. code plot can be seen in Figure 4. Zero-Code Error Drift This is a measure of the change in zero-code error with a change in temperature. It is expressed in V/C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV secs and is measured when the digital input code is changed by 1 LSB at the major carry transition (7FFF Hex to 8000 Hex). See Figure 19. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV secs and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa.
Rev. PrB | Page 8 of 17
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
AD5601/AD5611/AD5621
Figure 4. Typical INL Plot
Figure 7. Typical DNL Plot
Figure 5. Total Unadjusted Error Plto.
Figure 8. INL and DNL vs Supply
Figure 6. Zero Scale Error and Full Scale Error vs. Temperature
Figure 9. IDD Histogram @ VDD = 3 V/5 V
Rev. PrB | Page 9 of 17
AD5601/AD5611/AD5621
Preliminary Technical Data
Figure 10. Source and Sink Current Capability
Figure 13. Supply Current vs Code.
Figure 11. Supply Current vs. Temperature
Figure 14. Supply Current vs. Supply Voltage
Figure 12. Full Scale Settling Time
Figure 15. Half Scale Settling Time
Rev. PrB | Page 10 of 17
Preliminary Technical Data
AD5601/AD5611/AD5621
Figure 16. Power on Reset to 0 V
Figure 19. Exiting Power-Down
Figure 17. Digital to Analog Glitch Impulse
Figure 20. Harmonic Distortion on Digitally Generated Waveform.
Figure 18. Output Spectral Density 100k Bandwidth
Figure 21. 0.1 Hz to 10 Hz Noise Plot
Rev. PrB | Page 11 of 17
AD5601/AD5611/AD5621 GENERAL DESCRIPTION
D/A SECTION
The AD5601/AD5611/AD5621 DACs are fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 22 shows a block diagram of the DAC architecture.
VDD REF (+) DAC REGISTER RESISTOR NETWORK REF (-) OUTPUT AMPLIFIER VOUT
Preliminary Technical Data
SERIAL INTERFACE
The AD5601/AD5611/AD5621 have a three-wire serial interface (SYNC, SCLK and DIN), which is compatible with SPI, QSPI and MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 16-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5601/AD5611/AD5621compatible with high speed DSPs. On the 16th falling clock edge, the last data bit is clocked in and the programmed function is executed (i.e., a change in DAC register contents and/or a change in the mode of operation). At this stage, the SYNC line may be kept low or be brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Since the SYNC buffer draws more current when VIN = 1.8 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation of the part, as mentioned above; however, it must be brought high again just before the next write sequence.
GND
Figure 22. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal output voltage is given by
where D = decimal equivalent of the binary code that is loaded to the DAC register.
RESISTOR STRING
The resistor string section is shown in Figure 21. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
04611-A-022
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 23). The first two bits are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). There is a more complete description of the various modes in the Power-Down Modes section. The next sixteen bits are the data bits. These are transferred to the DAC register on the 16th falling edge of SCLK.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 V to VDD. It is capable of driving a load of 2 k in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 9 and Figure 10. The slew rate is 0.5 V/s with a half-scale settling time of 8 s with the output unloaded.
DB15 (MSB) PD1 PD0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 DBO (LSB) D1 D0
DATA BITS
1 1
0 1
100 k TO GND THREE-STATE
POWER-DOWN MODES
Figure 23. Input Register Contents
Rev. PrB | Page 12 of 17
04611-A-023
0 0
0 1
NORMAL OPERATION 1 k TO GND
Preliminary Technical Data
SCLK
AD5601/AD5611/AD5621
SYNC
04611-A-024
DIN
DB15
DB0
DB16
DB0
INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 16TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 16TH FALLING EDGE
Figure 24. SYNC Interrupt Facility
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents or a change in the operating mode occurs--see Figure 24.
the part is in power-down mode. There are three different options. The output is connected internally to GND through a 1 k resistor or a 100 k resistor, or is left open-circuited (three-state). Figure 25 shows the output stage.
RESISTOR STRING DAC
AMPLIFIER
VOUT
POWER-ON-RESET
The AD5601/AD5611/AD5621 contains a power-on-reset circuit that controls the output voltage during power-up. The DAC register is filled with zeros and the output voltage is 0 V. It remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up.
Figure 25. Output Stage During Power-Down
POWER-DOWN MODES
The AD5601/AD5611/AD5621 contain four separate modes of operation. These modes are software-programmable by setting two bits (DB17 and DB16) in the control register. Table 5 shows how the state of the bits corresponds to the mode of operation of the device. Table 5. Modes of Operation for the AD5601/AD5611/AD5621
DB15 0 0 1 1 DB14 0 1 0 1 Operating Mode Normal Operation Power-Down Mode 1 k to GND 100 k to GND Three-State
The bias generator, the output amplifier, the resistor string and other associated linear circuitry are all shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 2.5 s for VDD = 5 V and 5 s for VDD = 3 V. See Figure 18 for a plot.
MICROPROCESSOR INTERFACING
AD5601/AD5611/AD5621 to ADSP-2101/ADSP-2103 Interface
Figure 26 shows a serial interface between the AD5601/AD5611/AD5621 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in SPORT transmit alternate framing mode. The ADSP2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled.
When both bits are set to 0, the part works normally with its normal power consumption of 100 A max at 5 V. However, for the three power-down modes, the supply current falls to <100 nA at 3 V). Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while
Figure 26. AD5601/AD5611/AD5621 to ADSP-2101/ADSP-2103 Interface
AD5601/AD5611/AD5621 to 68HC11/68L11 Interface
Rev. PrB | Page 13 of 17
04611-A-025
POWER-DOWN CIRCUITRY
RESISTOR NETWORK
AD5601/AD5611/AD5621
Figure 27 shows a serial interface between the AD5601/AD5611/AD5621 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5601/AD5611/AD5621, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the AD5601/AD5611/AD5621, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure.
Preliminary Technical Data
AD5601/AD5611/AD5621 to 80C51/80L51 Interface
Figure 29 shows a serial interface between the AD5601/AD5611/AD5621 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TXD of the 80C51/80L51 drives SCLK of the AD5601/AD5611/AD5621, while RXD drives the serial data line of the part. The SYNC signal is again derived from a bit programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the AD5601/AD5611/AD5621, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD5601/AD5611/AD5621 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account.
Figure 27. AD5601/AD5611/AD5621 to 68HC11/68L11 Interface Figure 29. AD5601/AD5611/AD5621 to 80C51/80L51 Interface
AD5601/AD5611/AD5621 to Blackfin(R) ADSP-BF53X Interface
Figure 28 shows a serial interface between the AD5601/AD5611/AD5621 and the Blackfin ADSP-53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5601/AD5611/AD5621, the setup for the interface is as follows: DT0PRI drives the SDIN pin of the AD5601/AD5611/AD5621, while TSCLK0 drives the SCLK of the part. The SYNC is driven from TFS0.
AD5601/AD5611/AD5621 to MICROWIRE Interface
Figure 28 shows an interface between the AD5601/AD5611/AD5621 and any MICROWIRE compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5601/AD5611/AD5621 on the rising edge of the SK.
Figure 30. AD5601/AD5611/AD5621 to MICROWIRE Interface
Figure 28. AD5601/AD5611/AD5621 to Blackfin ADSP-BF53X Interface
Rev. PrB | Page 14 of 17
Preliminary Technical Data APPLICATIONS
CHOOSING A REFERENCE AS POWER SUPPLY FOR AD5601/AD5611/AD5621
The AD5601/AD5611/AD5621 comes in a tiny SC70 package with less than 100 A supply current. Because of this, the choice of reference depends on the application requirement. For space saving applications, the ADR425 is available in an SC70 package and has excellent drift at 3ppm/C. It also provides very good noise performance at 3.4 V p-p in the 0.1 Hz to 10 Hz range. Because the supply current required by the AD5601/AD5611/AD5621 is extremely low, it is ideal for low supply applications. The ADR293 voltage reference is recommended in this case. This requires 15 A of quiescent current and can therefore drive multiple DACs in the one system if required.
AD5601/AD5611/AD5621
BIPOLAR OPERATION USING THE AD5601/AD5611/AD5621
The AD5601/AD5611/AD5621 has been designed for singlesupply operation, but a bipolar output range is also possible using the circuit in Figure 32. The circuit in Figure 32 will give an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as follows:
where D represents the input code in decimal (0-2N). With VDD = 5 V, R1 = R2 = 10 k:
This is an output voltage range of 5 V with 0000Hex corresponding to a -5 V output and 3FFF Hex corresponding to a +5 V output.
Figure 31. ADR425 as Power Supply to AD5601/AD5611/AD5621
Examples of some recommended precision references for use as supply to the AD5601/AD5611/AD5621 are shown in Table 6. Table 6. Precision References for Use with AD5601/AD5611/AD5621
Initial Accuracy (mV max) 6 6 5 6 Temperature Drift (ppm/C max) 3 3 3 25 0.1-10 Hz Noise (V p-p typ) 3.4 3.4 15 5
Figure 32. Bipolar Operation with the AD5601/AD5611/AD5621
Part No. ADR435 ADR425 ADR02 ADR395
Rev. PrB | Page 15 of 17
AD5601/AD5611/AD5621
USING AD5601/AD5611/AD5621 WITH AN OPTOISOLATED INTERFACE
In process-control applications in industrial environments, it is often necessary to use an opto-isolated interface to protect and isolate the controlling circuitry from any hazardous commonmode voltages that may occur in the area where the DAC is functioning. Opto-isolators provide isolation in excess of 3 kV. Because the AD5601/AD5611/AD5621 uses a 3-wire serial logic interface, it requires only three opto-isolators to provide the required isolation (see Figure 33). The power supply to the part also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5601/AD5611/AD5621.
Preliminary Technical Data
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5601/AD5611/AD5621 should have separate analog and digital sections, each having its own area of the board. If the AD5601/AD5611/AD5621 is in a system where other devices require an AGND to DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5601/AD5611/AD5621. The power supply to the AD5601/AD5611/AD5621 should be bypassed with 10 F and 0.1 F capacitors. The capacitors should be physically as close as possible to the device with the 0.1 F capacitor ideally right up against the device. The 10 F capacitors are the tantalum bead type. It is important that the 0.1 F capacitor has low effective series resistance (ESR) and effective series inductance (ESI), e.g., common ceramic types of capacitors. This 0.1 F capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.
Figure 33. AD5601/AD5611/AD5621 with an Opto-Isolated Interface
Rev. PrB | Page 16 of 17
Preliminary Technical Data OUTLINE DIMENSIONS
2.00 BSC
6 5 2 4
AD5601/AD5611/AD5621
1.25 BSC
1 3
2.10 BSC
PIN 1 1.30 BSC 1.00 0.90 0.70 0.65 BSC 1.10 MAX 0.22 0.08 0.30 0.15 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203AB SEATING PLANE 8 4 0
0.10 MAX
0.46 0.36 0.26
Figure 34. 6-Lead Plastic Surface Mount Package [SC70] (KS-6) Dimensions shown in millimeters
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
PR04783-0-4/04(PrB)
Rev. PrB | Page 17 of 17

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